In a typical multi-layer and/or multi-level interconnect system, peripherals, memory, and/or other slave components are addressed by a master component (e.g., processor, server, interface device, etc.) using a system memory map. As is well known, a memory map is essentially a data structure, often residing in memory itself, which is used for defining how an operating system allocates (i.e., shares) the main memory space in the system.
In general, some peripherals are specific to a corresponding master, and other peripherals are shared among multiple masters. All masters and slaves generally interact with one another using defined bus protocols. Typical access logic between masters and slaves include protocol conversion, bus arbitration, peripheral address decoding, protection checks, etc. Unfortunately, conventional approaches to master/slave interaction are often complex and utilize significant area in an integrated circuit (IC), among other disadvantages.